Electrically, bipolar transistors can be thought of as two diodes back to back. The current flows from the emitter region through the base into the collector. When there is no current to the base, the transistor is turned off. When it is on, the current flows. It only takes a small current to turn the base on enough to allow current flow through the entire transistor.
Most bipolar circuits are designed with NPN transistors. NPN represents the respective conductivity types of the emitter, base, and collector. Bipolar transistors feature fast switching speeds. The speed and performance of a bipolar transistor is governed by a number of factors, including vertical base dopant film thickness (base width), the base resistance (Rb), and the collector-base capacitance (Ccb). Cut-off frequency (fT) and maximum oscillation frequency (fmax) are the most representative measures of operation speed for high-speed transistors. Hence, the design and optimization efforts for high-speed transistors are mostly directed towards maximization of the aforementioned parameters.
The cut-off frequency (fT), a measure of current gain within the device, can be improved through vertically scaling the device, by decreasing the dimension from the emitter through the base to the collector. The cut-off frequency (fT), may also be increased by running the device at higher currents. One way to run a higher current is by laterally scaling the device, where the emitter has a smaller lateral dimension. Lateral scaling provides a high current density without having to increase the absolute current through the device; therefore, allowing for operating the device at an even higher cut off frequency (fT). Additionally, the cut-off frequency (fT) may also be increased by increasing the amount of dopant in the collector in order to offset the Kirk effect.
The above modifications, which may increase the cut off frequency (fT), may also increase parasitic effects within the device, disadvantageously effecting the maximum oscillation frequency (fmax). The maximum oscillation frequency f also referred to as the power gain unity cut off frequency, is a measurement of power gain as opposed to cut off frequency (fT), which is a measurement of current gain. The terms “parasitic elements of the device” are defined as the difference between an ideal NPN device and any additional values produced in providing a practical implementation of the ideal device. The parasitic effects of the device may include the parasitic portions of base resistance (Rb), collector resistance (Rc), collector-emitter capacitance (Cce), collector-base capacitance (Ccb), and collector-substrate capacitance (Ccs). In addition to the above parasitics, the parasitic elements of the emitter-base capacitance (Ceb) and the emitter resistance (Re) may also disadvantageously affect the cut off frequency (fT) and maximum oscillation frequency (fmax), particularly at low current.
Currently, in NPN devices, one or more parasitic elements could be reduced by existing production means but disadvantageously at the expense of other increased parasitic effects resulting in a decreased performance device overall. For example, referring to the prior NPN BJT (bipolar junction transistor) structure depicted in FIG. 1, a reduction in the parasitic base resistance for a given emitter region size may involve forming the extrinsic base 15 in close proximity to an intrinsic portion 16 of the device by reducing the width of the spacer 14. The terms “intrinsic portion of the device” are meant to denote the portions of the device forming the NP and PN junctions of the NPN bipolar transistor, for example, which include the intrinsic emitter, intrinsic base, and intrinsic collector. Extrinsic portions of the device provide electrical communication to the intrinsic portions of the device. With close proximity of the extrinsic base 15 to the intrinsic base, the base resistance (Rb) may be reduced. But bringing the extrinsic base 15 in close proximity to the intrinsic portion 16 of the device increases the parasitic collector-base capacitance (Ccb), which is produced by the interaction between the highly doped extrinsic base 15 and the collector pedestal region 17. The parasitic collector-base capacitance (Ccb) may be minimized by reducing the dopant in the portion of extrinsic base 15 that is in closest proximity to the collector pedestal 17, but reducing the dopant in the extrinsic base region 15 disadvantageously increases the parasitic base resistance (Rb). Therefore, a trade-off exists between the parasitic elements of the collector-base capacitance (Ccb) and the base resistance (Rb).
Still referring to the prior art transistor structure depicted in FIG. 1, a parasitic emitter-base capacitance (Ceb) is disadvantageously present between the contact pad portion 19 of the emitter 18 and the extrinsic base 15. The contact pad 19 is a portion of the emitter, which extends above and overlies a portion of the extrinsic base regions 15 upper surface. In prior transistors, the contact pad portion 19 was necessary to ensure electrical contact to the emitter 18. The contact pad 19 also disadvantageously contributes to the parasitic emitter resistance (Re) by increasing the extrinsic portion of the emitter 18 without simultaneously creating an electrical short to the extrinsic base 15, particularly in the case of contact misalignment during processing. Additionally, the contact pad portion 19 of the emitter 18 increases the parasitic base resistance (Rb) by extending atop a portion of the extrinsic base 15 resulting in a highly resistive region 22 of the extrinsic base 15, which can not be silicided.
U.S. patent Application No. 2003/0057458 provides one prior NPN transistor having a shallow junction raised extrinsic base, where increasing the distance between the collector pedestal and the extrinsic base reduces the collector-base capacitance (Ccb), but disadvantageously tends to increase the parasitic base resistance (Rb). Additionally, the emitter contains an emitter contact pad overlying a portion of the extrinsic base.
U.S. Pat. No. 6,346,453 provides another transistor having an emitter including an emitter contact pad portion that disadvantageously produces increased parasitic emitter-base capacitance (Ceb) and increased emitter resistance (Re). Additionally, a portion of the contact pad region of the emitter disclosed in U.S. Pat. No. 6,346,453 is positioned overlying the extrinsic base, where a non-silicided portion of the extrinsic base Her increases the parasitic base resistance (Rb).
U.S. Pat. No. 5,962,880 provides another example of a prior transistor having a large emitter structure and further incorporating a large isolation spacer between the emitter and the base, therefore producing a device where the parasitic portions of the base resistance (Rb), emitter-base capacitance (Ceb), and the emitter resistance (Rb) can not be reduced.
In view of tie drawbacks mentioned with prior art bipolar transistors, there is a need for developing a new and improved bipolar transistor in which the parasitic effects (resistances and capacitances) of the structure may be concurrently reduced in order to improve the transistor's high-speed performance.